Typically, a digital imager circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, e.g. a photogate, a photoconductor, or a photodiode. In a CMOS imager, a readout circuit connected to each pixel cell typically includes at least an output transistor. The photoconversion device converts photons to electrons which are typically transferred to a floating diffusion (FD) region, connected to the gate of a source follower output transistor. A charge transfer device can be included as well and may be a transistor for transferring charge from the photoconversion device to the floating diffusion region. Imager cells also typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
FIG. 1 illustrates a block diagram of a CMOS imager device 308 having a pixel array 200 containing a plurality of pixels arranged in rows and columns. The pixels of each row in array 200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. The row lines are selectively activated by a row driver 210 in response to row address decoder 220. The column select lines are selectively activated by a column selector 260 in response to column address decoder 270. The pixel array is operated by the timing and control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel signal readout. The pixel column signals, which typically include a pixel reset signal (Vrst) and a pixel image signal (Vsig), are read by a sample and hold circuit 261 associated with the column selector 260. A differential signal (Vrst−Vsig) is produced by differential amplifier 262 for each pixel which is amplified and digitized by analog to digital converter 275 (ADC). The analog to digital converter 275 supplies the digitized pixel signals to an image processor 280, which forms a digital image.
Each pixel of array 200 has a photosensor, e.g. a photogate, photodiode or other photoconversion element for generating electron/hole pairs in response to incident light. The generated electrons are collected in an n-type region of the photosensor. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion region and it may be transferred to the floating diffusion region via a transfer transistor. The charge at the floating diffusion region is typically converted to a pixel output voltage by the source follower transistor. A floating diffusion region is also used at the output stage of a CCD image sensor which receives transferred charges from photosensors of a pixel array.
One problem associated with imagers is the inability to fully store at a floating diffusion region all charge generated by a photosensor. In addition, the floating diffusion region typically loses some charge transferred to it. Such charge leakage can lead to poor signal to noise ratios, punch-through at a reset transistor gate used to reset the floating diffusion region to a known state prior to a charge transfer and poor dynamic range.